Make Munich 2019 – It’s been our pleasure

Make Munich 2019 was awesome. Thanks to everyone who helped making this great event possible.

Again, we are stunned by how much positive feedback we got from so many people. Thank you all!!

Also, like in 2016, our booth was partly turned by a lot of kids into the official Make Munich arcade. So we definitely need to write more games. And build more Steckschweins. Let the children play.

Posted in Allgemein

Meet us at Make Munich, 2.3. – 3.3.2019

Check out our homebrew 65c02 8bit goodness including our brand new video/sound-hardware at the Make Munich fair. We’ll also have BASIC, Forth, a couple of games and candy.
Our booth is in Hall 1, Booth Nr. 49, in the “Electronic Innovators”-Area. The did get that right, didn’t they?

 

 

 

Posted in Allgemein

Fixing the white screen problem on a Tekway DST1062B oscilloscope

The Tekway DST 1062B (also known unter the Hantek or Voltcraft brand) is an inexpensive 60MHz digital storage oscilloscope, which is very much hackable and has proven to be worth its weight in gold pressed latinum.

More recently, my scope became affected by the infamous white screen problem, which apparently is a problem quite common to this model and its 100MHz or 200MHz siblings.

white_screen

The Tekway/Hantek white screen of death

The screen just goes white, but the scope otherwise responds to pressing buttons, etc. so it appears not to be completely dead.
Some research revealed bad connections inside the scope as a possible culprit:
https://hackcorrelation.blogspot.com/2014/01/dso5062b-white-screen-repair-and-hack.html
But in my case, that did not do anything.
More research brought me to a couple of messages within the famous Tekway hacking thread on the EEVBlog-Forum:
https://www.eevblog.com/forum/testgear/hantek-tekway-dso-hack-get-200mhz-bw-for-free/msg87635/#msg87635

Forum member “bbf” told me during a conversation, that he had replaced the 3.3V regulator, but did not remember exactly, which regulator he used.
With this information, I went to examine the power supply. The 3.3V rail is powered by a KA78R33 regulator, which is rated for a maximum current of 1A. I removed it in order to power the 3.3V rail directly from my bench supply.

photo_2019-02-12_17-33-18

That’s a lot of load for the stock 3.3V regulator

And there we have it. The KA78R33 is under a constant load of almost 1.3A. Also using the bench supply I could play around with the exact voltage and I found out, that the scope is very sensitive about the voltage being correct. A voltage drop down to 3.2V will make the screen go white again.
To make things worse, the KA78R33 is completely potted in plastic, which I don’t imagine to be the best idea in terms of heat dissipation.
So we obviously need a beefier 3.3V regulator. I decided to go for a LM1085 which is rated for 3A, so we have plenty of safety margin. Also, it is almost pin compatible with the KA78R33, if inserted “the other way around”. Also, the LM1085 does not have GND but Vout on it’s housing, so one needs to be careful to not have it touch anything it’s not supposed to.
So with the new regulator, the scope works like a charm again.

Originally, the scope was sold as fanless, which was a big selling point for me back then. Inside, there happens to be a place to mount an 50mm 12V fan, also the power supply has a 12V rail just to power a fan. To be on the safe side from now on, I installed a fan. I just replaced the 12V regulator with a 9V one in order to keep fan noise down.

scope_ok_again

Posted in Allgemein

V9958+OPL2-Boards are there

The newly made boards made their way from China to Munich. Starting now, the multi board version of the Steckschwein is made up of 3 Boards: CPU/Memory, IO/UART and V9958-OPL2.

Posted in dram, kicad, layout, platinen, RGB, sound, V9958, vdp, video, video chip, ym3812

New V9958-Board with integrated OPL2

It’s time for another hardware upgrade. Since we really want to get our single board Steckschwein done, we are going for higher integration of our multiboard prototype. After integrating the UART to the IO-Board, we integrate the OPL2 sound part onto the V9958 video board, so the current Steckschwein multi board incarnations are reduced to three boards.
We did postpone our plan to upgrade sound to OPL3 because Daniel Illgen, which we met at VCFb, convinced us with some awesome OPL2 tunes that OPL2 is still cool. Also, we save the extra oscillator, since the OPL2 can be clocked using the CPUCLK-Pin from the V9958, which happens to provide 3.58MHz.

We did upgrade however the video ram. The first prototype had Bank 0 and Bank 1, maxing out vram at 128k. We decided to include the Extended memory bank, too, this time, giving the V9958 extra 64k, which can be accessed using the blitter command functions. Why not?

v9958

KiCad 3D rendering of the new board

Also, to make the connector side more compact, we decided to not use RCA jacks for RGB anymore, but an 8pin DIN jack, which also carries the audio signal. So hooking up a 1084 Monitor or TV will only require a single cable. We use the same DIN jack and pinout as the NeoGeo uses, so there are even ready made cables available.

 

Posted in kicad, layout, opl2, platinen, RGB, SCART, sound, V9958, video, video chip, video signal, ym3812

V9958 – “The WAIT” – investigation of the CPU/VDP /WAIT interface

… on the way back to munich, we had some time to do a little code review of our gfx library. thinking about the cpu to video chip timings and again read the well known datasheets of the V9938/V9958. suddenly i got an enlightenment and we came to the following conclusion.

as described in the datasheet (V9958-Technical-manual_v1.0.pdf) of the V9958 there are different timings given for different kind of writes. so as far as we understand there are the following timings

  1. the first 2 bytes send to vdp during a write are always register writes which require a short delay of at least 2µs in between each byte
  2. the write of the 3rd byte (after the 2nd) requires a delay of 8µs. any further “single byte transfer” – during a vram write – also requires the 8µs delay. the same is true if we want to initiate a register write direclty after a vram write.
  3. the 3rd and n-th byte write to port #3 (index register port) during a bulk register write requires only the 2µs between each byte

With this in mind, we can optimize our library a little bit by using different “nop slides” for address setup and vram writes.

We enhance our vdp.inc and built two macros which provide the different delay we need.

.macro vdp_wait_s
  jsr vdp_nopslide_2m ; 2m for 2µs wait
...

.macro vdp_wait_l
  jsr vdp_nopslide_8m ; 8m for 8µs wait
...

steckSchwein is running at 8Mhz, so we also defined some equations and used ca65 macros to build our nop slides.

.define CLOCK_SPEED_MHZ 8

; long delay with 6µ+2µs (below)
MAX_NOPS_8M = (6 * 1000 / (1000 / CLOCK_SPEED_MHZ)) / 2 
; 8Mhz, 125ns per cycle, wait 6µs = 6000ns 
; = 6000ns / 125ns = 48cl / 2 => 24 NOP 

; short delay with 2µs wait
MAX_NOPS_2M = (2 * 1000 / (1000 / CLOCK_SPEED_MHZ) -12) / 2 
; -12 => jsr/rts = 2 * 6cl = 12cl must be subtract

.macro m_vdp_nopslide
vdp_nopslide_8m:
   ; long delay with 6+2 2µs wait
   .repeat MAX_NOPS_8M
      nop
   .endrepeat
vdp_nopslide_2m:	
   .repeat MAX_NOPS_2M
      nop
   .endrepeat
   rts
.endmacro

Another interesting thing would be, “how does the /WAIT” behave in this situation? the assumption here is, that the /WAIT will behave in the way as specified. so /WAIT will be go low at least after 130ns from CSW. so to handover the /RDY handling to the vdp via the /WAIT pin, we have to apply only 1 wait state from our WS-Gen. after one wait state, we can release the /RDY low from our WS so that the vdp /WAIT can drive /RDY as needed.

Back home, Thomas did the test and changed the waitstate generator firmware for the GAL16V8.

The equation was

W2 = ROM * UART * SND * /VDP 
W1 = W2 
     + /ROM * UART * VDP

and was changed to

W2 = /SND
W1 = W2
     + /ROM 			; /ROM wait state if ROM is cs
     + /VDP			; /VDP wait state if VDP is cs

So finally, we only need one wait state from the waitstate generator to access the VDP. If the VDP requires more time – surely – during a video memory access it will drive /WAIT to low as long as needed. So after the explcit 1WS from our wait state generator we now hand over the /RDY control to the VDP. How our /RDY and /WAIT really work together is subject to one of our next sessions where we’re going to measure the things with a logic analyzer and oscilloscope. Nevertheless, it works in this way and it works exaclty as specified within the datasheet.

Posted in 64k, 6502, 65c02, 9918, Allgemein, assembly, cpu, experiment, nop, steckschwein, timing, tms9929, V9958, vdp, video, video chip, waitstate

VCFB 2018 It was great…

VCF 2018 in Berlin was great! We’ve met interesting people there. Got a handshake with Scot W. Stevenson who for(th)ced us to use his TaliForth2 😉

Later on Saturday Daniel Illgen – maintainer of the Adlib Tracker II for Linux – had decided to honor us with his OPL2 knowledge while on the way out. He advised us to keep the OPL2 sound chip on the Steckschwein, because the OPL2 chip is still not outbid. We hat doubts at first, but then we could listen to OPL2 with so called “software low frequency oscillation” (soft lfo) and the drums and bass sounds great!

Beside the VCF there where talks about demos and the history of the demoscene then and now. There where two interesting and awesome talks given by “SvOlli” about the demoscene and demo coding on the Atari VCS (Stella).

Here are the slides of out talks and Links to the livestream from Saturday 13.10.2018.

Many thanks to Dr. Stefan Höltgen and his team arround the VCFB which made it possible that we could take a part on that cool event!

Posted in Allgemein, assembly, code, cpu, debugging, py65mon, quality, software, stackpointer, steckschwein, Steckschwein live, tests, unit tests