VCFe25.0
VCFe25.0 has been awesome, as always. This time, all the talks have been recorded and will be available soon.
The slides for our talk about our ATF150x toolchain are available here
The Steckschwein is a homebrew 8bit computer based on the 65c02 CPU.
The Idea
The project began with a simple idea: create an 8‑bit computer that feels like it came straight out of the home‑computer era, yet works comfortably in today’s world. So instead of floppy disks, the system uses SD cards via SPI, blending classic design with modern convenience.
We started by using genuine period‑correct chips to stay as close as possible to the machines of that time. As those components have become harder to find, we’re gradually introducing modern replacements—always with the goal of preserving the original spirit.
The Name
The name “Steckschwein” comes from our breadboard beginnings—Steckbrett in German. With all those unruly wires, the prototypes behaved like little pigs, so the name stuck.
The Specs
| Component | Specification |
|---|---|
| CPU | 65c02-CPU @ 10MHz |
| Memory | 512k SRAM / 512k Flash EEPROM |
| Storage | SD-Card (SPI) |
| Serial (rs232) | UART 16550 |
| IO | VIA 65c22 (2 Atari Joystick Ports + SPI (bit banged)) |
| Video | V9958 |
| Sound | YM3812 (OPL2) |
| Keyboard | PS/2 via ATmega8 over SPI |
| RTC | Maxim DS1306 |
Further reading and more details on Steckschwein Hardware.
The Story so far
It all started with a NOP. We put a 65C02 CPU on a breadboard and hard‑wired its data bus to $EA — the 6502’s NOP instruction, meaning “no operation.” The address bus was connected to LEDs, and the CPU clock ran at about 1 kHz. The question was simple: would the LEDs show something that looked like binary counting?
The photo series below highlights several milestones from the past years. For more detailed information about our development steps and processes, please visit our Blog.
UART: Double Trouble
The DUART TL16c2752 is supposed to be a rather big upgrade to the Steckschwein “core”. Now two serial interfaces, with 64 byte FIFOs each, instead of only one interface with 16 byte FIFOs. Oh, the possibilities. Using one line to explore UART interrupt handling while still having another one to upload code. Cool!
With the 16C2752 being a part of the 16C550 family, we did expect it to be a simple drop in replacement for the latter one. As we all know, happiness is reality minus expectation, and oh boy did things get dreadful!
Prototype with ATF1508 on Breadboard [UPDATE II]
We are going back to breadboarding for designing what will be the base for the new Steckschwein computer core. By “core” we mean CPU, RAM, ROM and the glue logic which will be accommodated in the ATF1508 CPLD. In order to communicate with the outside word, we also count the 16C550 UART as part of the core.
Design goals
Our main design goals are:
- Integrate SPI into the CPLD -> DONE
Using a hardware based SPI implementation similiar to Daryl Rictor’s SPI65, but tightly integrated into the CPLD will be an efficient use of the CPLD resources and will provide a much more performant SPI bus as opposed to the current semi-bit-banged solution. This way, it will be much more performant to add more SPI based components such as USB host or networking (see below).
Update: Done! We decided to use Andre Fachat’s SPI implementation from his MicroPET. The main advantage over rolling our own is - it’s already there. Another main advantage over other existing Implementation is that the MicroPET one is pretty small, which is important when CPLD resources are at a premium. - Implement a priorising vectorising interrupt controller
This will improve interrupt handling by assigning a dedicated ISR routine per interrupt source instead of one system ISR.
Update: We are already scratching the limit of the ATF1508. The PLCC84 version we use in our prototype can not handle more pins, so we are unable to add the inputs needed for all the interrupt sources we need. While this is unfortunate, we have not scrapped the idea of an interrupt controller. We might move to the TQFP-100 version at some point, which obviously has more pins. - DUART instead of UART
Replacing our trusty 16C550 with a 16C2752 DUART will provide two serial interfaces without increasing the chip count.
With two serial ports, we will be able to upload programs on one serial port, while observing the output on the other one. Also, a separate upload interface will allow us to explore UART interrupts on the other.
Other changes/optimizations
Other things that will be optimized are:
CPLD Upgrade and new Toolchain
Since we introduced our new banking logic to access 512k RAM, our glue logic is being accommodated by a Xilinx XC9572 (without XL) CPLD. This component has long been deprecated when we started using it. We chose it because it was what we had available. The upgrade path would be the successor family XC95..XL. Those have been rather expensive lately, and finally AMD/Xilinx axed their whole CPLD line in 2024, leaving us at a dead end. Where do we go from here? The market for CPLDs is not exactly growing. Only a few manufacturers are still actively producing them.
Golem.de Podcast featuring Steckschwein
Finished moving to codeberg.org
After we moved this website to Codeberg Pages, we now finished moving our Repositories to www.codeberg.org.
The resources page has been updated with the new URLs.
Our repositories on GitHub will remain available as push mirrors, but may vanish at some point.
Codeberg is a non-profit, community-led effort that provides Git hosting and other services for free and open source projects.