Just in time for VCFe 22.0 our new SBC boards have arrived! Be there at VCFe, when we are assembling the new Steckschwein SBC and have a few beers with us! Save the date(s): 29.4. - 1.5.2023 ESV München OST, now at Hermann-Weinhauser-Straße 7 81673 München Check it out: https://vcfe.org/

Looks like the upcoming VCFe 22.0 will be a feast for the 6502-connoisseur: Andre Fachat will show his MicroPET and his 6502 multitasking operating system “GeckOS”, Armin Hierstetter will show an authentic Apple I replica, and of course we will be there, too, showing our new banking schema and our emulator. Save the date(s): 29.4. - 1.5.2023 We really are looking forward to a glorious VCFe, which will also be back at the new old location, the sports hall of the ESV München OST, now at

This one really is a tough one to debug. At first, we suspected the VHDL code for the CPLD as the main error source, as VHDL is not our strongest suit. In fact, the decoder/banking logic is the first thing we ever really did in VHDL (apart from a few simple decoder equations the first days we were playing with GALs). As it turned out, the VHDL was not the main problem.

In preparation for the build of our new CPU-Board, we purchased two WDC 65c02 in PLCC44 package from some eBay vendor. On arrival, the first interesting thing is the way they were packaged. No anti esd packaging, only a plastic bag, which we found sketchy enough to post on Twitter. Next, WDC reacted to that tweet, stating that these might be not genuine or be at least very old. So much for ESD safe packaging pic.

The biggest limitation of any 8 bit CPU such as our beloved 65C02 is the amount of memory that the CPU can address. With 16 address lines, the addressable memory is maxed out at 64k. All ROM and RAM has to be crammed into there. With the 6502 being a memory mapped architecture, IO devices need their addresses there, too. In order to expand the amount of usable memory, some trickery is necessary.